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Recent Cadence News:
TSMC Certifies Cadence Tempus Timing Signoff Solution for 20nm Designs - Wed, 22 May 2013
Cadence Design Systems, Inc. , a leader in global electronic design innovation, announced today that TSMC has certified the new Cadence® Tempus™ Timing Signoff Solution at 20 nanometers. The certification ...
Cadence Characterization Solution for Complex Multi-Bit Cells Delivers Power and Performance Benefits for Yamaha - Mon, 13 May 2013
Cadence Design Systems today announced that it helped Yamaha Corporation reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic ...
Cadence Introduces the Tempus Timing Signoff Solution, Delivering Unprecedented Performance and Capacity in Design ... - Mon, 20 May 2013
Cadence Design Systems, Inc.
Cadence launches massively parallel timing tool to speed SoC design - Mon, 20 May 2013
 Cadence Design Systems has launched a new static timing analysis and closure tool designed to run on passively parallel hardware and enable System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly.
TSMC certifies Cadence Design Tempus Timing Signoff Solution for 20mm designs - Wed, 22 May 2013
Cadence Design announced that TSMC has certified the new Cadence Tempus Timing Signoff Solution at 20 nanometers. The certification means the Cadence Tempus Timing Signoff Solution passes TSMC's rigorous ...